Semiconductor package and methods of manufacturing the same

ABSTRACT

A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from the first pad, a first external terminal formed on the first conductive layer pattern, a second insulation layer pattern formed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal and having a third opening in communication with the second opening, a second conductive layer pattern elongated along the second insulation layer pattern from the second pad, and a second external terminal formed on the second conductive layer pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 2006-105972, filed on Oct. 31, 2006 in the KoreanIntellectual Property Office, the contents of which are incorporatedherein by reference in their entirety.

BACKGROUND

1. Technical Field

Example embodiments of the present invention relate to a semiconductorpackage and methods of manufacturing the same. More particularly,example embodiments of the present invention relate to a wafer-levelpackage and methods of manufacturing the same.

2. Description of the Related Art

Generally, a plurality of semiconductor chips are formed by performingvarious semiconductor processes on a semiconductor substrate. To mounteach of the semiconductor chips on a mother-board, a packaging processis performed on the semiconductor substrate.

According to a conventional packaging process, a semiconductor substrateis cut along a scribe lane to separate the semiconductor substrate intoa plurality of semiconductor chips. After attaching the semiconductorchip on a printed substrate, bonding pads of the semiconductor chip areelectrically connected to the printed substrate using a conductive wire,or the like. A mold is formed on the printed substrate to surround thesemiconductor substrate with the mold, and external terminals such assolder balls are mounted on the printed substrate.

However, because the conventional packaging process is individuallyperformed on each of the semiconductor chips, the efficiency of theconventional packaging process may be very low.

To solve the above-mentioned problems, a wafer-level packaging processhas recently been suggested in which a semiconductor substrate is cutafter a packaging process is carried out on an entire surface of thesemiconductor substrate.

In the conventional wafer-level package, external terminals are arrangedon substantially the same plane. That is, the external terminals have asingle-layered structure. The external terminals have the single-layeredstructure, because pads of a board on which the wafer-level packages aremounted are on substantially the same plane. In other words, since thepads in electrical contact with the external terminals are arranged onsubstantially the same plane, the external terminals may have asingle-layered structure.

However, the external terminals of the wafer-level package are insertedinto the board in recently preferred technologies in order to increasethe bonding strength between the wafer-level package and the board.Thus, slots for receiving the external terminals are formed at a surfaceportion of the boards. The pads of the board are arranged around theslot.

However, because the conventional wafer-level package has thesingle-layered external terminals, the conventional wafer-level packagemay have a large size in order to avoid an electrical short between theexternal terminals. Specifically, to ensure reliable electricalconnections between the external terminals and the pads of the board,the board is required to have a relatively large size. That is, sincethe pads are arranged around the slots to avoid an electrical shortbetween the pads, the size of the board, on which each of the padscorresponding to the external terminals is arranged, may be large. Thepresent invention addresses these and other disadvantages of theconventional art.

SUMMARY

Example embodiments of the present invention provide a semiconductorpackage having a small size that is capable of preventing an electricalshort between external terminals. Example embodiments of the presentinvention also provide a method of manufacturing the above-mentionedsemiconductor package.

According to one aspect of the present invention, a semiconductorpackage includes a semiconductor chip, a first insulation layer pattern,a first conductive layer pattern, a first external terminal, a secondinsulation layer pattern, a second conductive layer pattern, and asecond external terminal. The semiconductor chip has first and secondpads. The first insulation layer pattern is formed on the semiconductorchip. Further, the first insulation layer pattern has first and secondopenings that expose the first and the second pads, respectively. Thefirst conductive layer pattern is elongated along the first insulationlayer pattern from the first pad. The first external terminal is formedon the first conductive layer pattern. The second insulation layerpattern is formed on the first conductive layer pattern and the firstinsulation layer pattern to expose the first external terminal. Further,the second insulation layer pattern has a third opening in communicationwith the second opening. The second conductive layer pattern iselongated along the second insulation layer pattern from the second pad.The second external terminal is formed on the second conductive layerpattern.

According to an aspect of the present invention, a semiconductor packageincludes a semiconductor chip, a first insulation layer pattern, a firstconductive layer pattern, a first external terminal, a second insulationlayer pattern, a second conductive layer pattern, and a second externalterminal. The semiconductor chip has first and second pads. The firstinsulation layer pattern is formed on the semiconductor chip. Further,the first insulation layer pattern has first and second openings thatexpose the first and the second pads, respectively. The first conductivelayer pattern is elongated along the first insulation layer pattern fromthe first pad. The first external terminal is formed on the firstconductive layer pattern. The second insulation layer pattern is formedon the first conductive layer pattern and the first insulation layerpattern to expose the first external terminal. Further, the secondinsulation layer pattern has a third opening in communication with thesecond opening. The second conductive layer pattern is elongated alongthe second insulation layer pattern from the second pad. The secondexternal terminal is formed on the second conductive layer pattern.

According to one example embodiment, the second external terminal may beplaced on a position higher than that on which the first externalterminal is positioned. Further, the second insulation layer pattern mayhave a protrusion higher than a surface of the first external terminal,and the second external terminal may be formed on the protrusion.

According to another aspect of the present invention, there is provideda method of manufacturing a semiconductor package. In the method ofmanufacturing the semiconductor package, a first insulation layerpattern having first and second openings that expose first and secondpads of a semiconductor chip is formed on the semiconductor chip. Afirst conductive layer pattern is elongated along the first insulationlayer pattern from the first pad. A first external terminal is thenformed on the first conductive layer pattern. A second insulation layerpattern having a third opening in communication with the second openingis formed on the first conductive layer pattern and the first insulationlayer pattern to expose the first external terminal. A second conductivelayer pattern is elongated along the second insulation pattern from thesecond pad. A second external terminal is then formed on the secondconductive layer pattern.

According to one example embodiment, forming the first insulation layerpattern may include forming a first insulation layer on thesemiconductor substrate, and etching the first insulation layer to formthe first insulation layer pattern having the first and the secondopenings.

Further, forming the first conductive layer pattern may include forminga first conductive layer on the first insulation layer pattern to fillup the first opening, and etching the first conductive layer to form thefirst conductive layer pattern.

Furthermore, forming the second insulation layer pattern may includeforming a second insulation layer on the first conductive layer patternand the first insulation layer pattern to cover the first externalterminal, partially removing a surface of the second insulation layer toform a second insulation structure having a protrusion higher than thefirst external terminal, and etching the second insulation structure toform the second insulation layer pattern having the third opening.

Moreover, forming the second conductive layer pattern may includeforming a second conductive layer on the second insulation layer patternto cover the second and the third openings, and etching the secondconductive layer to form the second conductive layer pattern.

According to some embodiments, the semiconductor package is manufacturedat a wafer level and the method further comprises separating thesemiconductor package from other semiconductor packages in a wafer afterforming the second external terminal.

According to another aspect of the present invention, a semiconductorpackage includes a semiconductor chip, a first insulation layer pattern,a first conductive layer pattern, a ground terminal, a second insulationlayer pattern, a second conductive layer pattern, and a signal terminal.The semiconductor chip has a ground pad and a signal pad. The firstinsulation layer pattern is formed on the semiconductor chip. Further,the first insulation layer pattern has first and second openings thatexpose the ground pad and the signal pad. The first conductive layerpattern is elongated along the first insulation layer pattern from theground pad. The ground terminal is formed on the first conductive layerpattern. The second insulation pattern is formed on the first conductivelayer pattern and the first insulation layer pattern to partially exposethe ground terminal. Further, the second insulation layer pattern has athird opening in communication with the second opening. The secondconductive layer pattern is elongated along the second insulation layerpattern from the signal pad. The signal terminal is formed on the secondconductive layer pattern.

According to one example embodiment, the signal terminal may be locatedon a position higher than that on which the ground terminal ispositioned. Further, the ground terminal may have a width wider thanthat of the signal terminal.

According to the present invention, the terminals have a stackedstructure so that the semiconductor package may have a relatively smallsize while preventing an electrical short between the terminals.Further, because pads of a board connected to the terminals may bealternately arranged around slots of the board, a size of the board maybe reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become readily apparent by reference to the following detaileddescription when considered in conjunction with the accompanyingdrawings, wherein:

FIG. 1 is a cross-sectional view illustrating a semiconductor package inaccordance with a first example embodiment of the present invention;

FIGS. 2 to 14 are cross-sectional views illustrating a method ofmanufacturing the semiconductor package in FIG. 1; and

FIG. 15 is a cross-sectional view illustrating a semiconductor packagein accordance with a second example embodiment of the present invention.

DETAILED DESCRIPTION

The present invention is described more fully hereinafter with referenceto the accompanying drawings, in which example embodiments of thepresent invention are shown. The present invention may, however, beembodied in many different forms and should not be construed as limitedto the example embodiments set forth herein. Rather, these exampleembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. In the drawings, the sizes and relative sizesof layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numbers refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the presentinvention. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Example embodiments of the present invention are described herein withreference to cross-sectional illustrations that are schematicillustrations of idealized embodiments (and intermediate structures) ofthe present invention. As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, example embodiments of thepresent invention should not be construed as limited to the particularshapes of regions illustrated herein but are to include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle will, typically, haverounded or curved features and/or a gradient of implant concentration atits edges rather than a binary change from implanted to non-implantedregion. Likewise, a buried region formed by implantation may result insome implantation in the region between the buried region and thesurface through which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Example Embodiment 1

FIG. 1 is a cross-sectional view illustrating a semiconductor package inaccordance with a first example embodiment of the present invention.

Referring to FIG. 1, a semiconductor package 100 in accordance with theexample embodiment may include a semiconductor chip 110, a firstinsulation layer pattern 130, a first conductive layer pattern 140, afirst external terminal 150, a second insulation layer pattern 160, asecond conductive layer pattern 170 and a second external terminal 180.

First and second pads 112 and 114 are formed on the surface of thesemiconductor chip 110. A passivation layer 120 is formed on the surfaceof the semiconductor chip 110. The first and the second pads 112 and 114are exposed through openings formed through the passivation layer 120.

The first insulation layer pattern 130 is formed on the passivationlayer 120. The first insulation layer pattern 130 has a first opening132 exposing the first pad 112 and a second opening 134 exposing thesecond pad 114. In the example embodiment of the present invention,examples of the first insulation layer pattern 130 may include a siliconoxide layer, a silicon nitride layer, and so on.

The first conductive layer pattern 140 is formed on the first insulationlayer pattern 130. The first conductive layer pattern 140 is formedalong the inner surface of the first opening 132 electrically connectedto the first pad 112. That is, the first conductive layer pattern 140has a first end electrically connected to the first pad 1 12, and asecond end elongated along the surface of the first insulation layerpattern 130 from the first end. In this example embodiment, an exampleof the first conductive layer pattern 140 may include a metal such asaluminum.

The first external terminal 150 is formed on the second end of the firstconductive layer pattern 140. The first external terminal 150 iselectrically connected to pads of a board on which the semiconductorpackage 100 is mounted. In this example embodiment, the board has a slotinto which the semiconductor package 100 is inserted. Further, the padsare arranged around the slots. In this example embodiment, examples ofthe first external terminal 150 may include solder, gold, copper, etcand the first external terminal 150 may be a conductive bump.

The second insulation layer pattern 160 is formed on the firstconductive layer pattern 140 and the first insulation layer pattern 130.In this example embodiment, to mount the first external terminal 150 onthe pad of the board, the first external terminal 150 is exposed fromthe second insulation layer pattern 160. The second insulation layerpattern 160 has a third opening 162 in communication with the secondopening 134. Accordingly, the second pad 114 is exposed through thesecond and third openings 134 and 162. Here, the second insulation layerpattern 160 has a protrusion 164 positioned adjacent to the firstexternal terminal 150. The protrusion 164 has a surface higher than thatof the first external terminal 150. Further, to reduce anelectromagnetic interference between the first external terminal 150 andthe second external terminal 180, a ferrite material or a ferromagneticmaterial may be used as the second insulation layer pattern 160.

The second conductive layer pattern 170 is formed on the secondinsulation layer pattern 160. The second conductive layer pattern 170 isformed along the inner surface of the second and the third openings 134and 162, and electrically connected to the second pad 114. In thisexample embodiment, the second conductive layer pattern 170 has a firstend electrically connected to the second pad 114, and a second endelongated along the surface of the second insulation layer pattern 160from the first end to the protrusion 164. In this example embodiment, anexample of the second conductive layer pattern 170 may include a metalsuch as aluminum.

The second external terminal 180 is formed on the second end of thesecond conductive layer pattern 170. The second external terminal 180may have a size substantially the same as that of the first externalterminal 150. The second external terminal 180 is positioned above theprotrusion 164 of the second insulation layer pattern 160. Thus, sincethe second external terminal 180 is located above the first externalterminal 150, the first and the second external terminals 150 and 180form a two-layered structure. Therefore, the first and the secondexternal terminals 150 and 180 precisely make contact with the pads ofthe board without an electrical short between the first and the secondexternal terminals 150 and 180. Alternatively, external terminals mayhave at least a three-layered structure using additional insulationlayer patterns. In this example embodiment, examples of the secondexternal terminal 180 may include solder, gold, copper, etc. and thesecond external terminal 180 may be a conductive bump.

FIGS. 2 to 14 are cross-sectional views illustrating a method ofmanufacturing the semiconductor package in FIG 1.

Referring to FIG. 2, the semiconductor chip 110 having the first pad 112and the second pad 114 is prepared. The semiconductor chip 110 is amonga plurality of semiconductor chips provided on a single wafer, with eachof the plurality of semiconductor chips similar to the semiconductorchip 110 shown in FIG. 2. The passivation layer 120 is formed on thesemiconductor chip 110 to expose the first and the second pads 112 and114 through the passivation layer 120.

Referring to FIG. 3, a first insulation layer 136 is formed on thepassivation layer 120. Examples of the first insulation layer 136 mayinclude a silicon oxide layer, a silicon nitride layer, etc.

Referring to FIG. 4, the first insulation layer 136 is etched to formthe first insulation layer pattern 130 having the first and secondopenings 132 and 134. In this example embodiment, a photoresist pattern(not shown) is formed on the first insulation layer 136. The firstinsulation layer 136 is etched using the photoresist pattern as anetching mask to form the first insulation layer pattern 130 having thefirst and the second openings 132 and 134. The first pad 112 is exposedthrough the first opening 132, and the second pad 114 is exposed throughthe second opening 134.

Referring to FIG. 5, a first conductive layer 142 is formed on the innersurfaces of the first insulation layer pattern 130 and the first andsecond openings 132 and 134. In this example embodiment, a metal such asaluminum may be used as the first conductive layer 142.

Referring to FIG. 6, the first conductive layer 142 is partially removedto form the first conductive layer pattern 140 elongated along thesurface of the first insulation layer pattern 130 from the first pad112. Here, the first conductive layer pattern 140 has the first endconnected to the first pad 112 and the second end elongated along thesurface of the first insulation layer pattern 130 from the first end.

Referring to FIG. 7, the first external terminal 150 is formed on thesecond end of the first conductive layer pattern 140. Examples of thefirst external terminal 150 may include solder, gold, copper, etc andthe first external terminal 150 may be a conductive bump. Additionally,a reflow process may be performed on the first external terminal 150 toprovide the first external terminal 150 with a spherical shape.

Referring to FIG. 8, a second insulation layer 166 is formed on thefirst insulation layer pattern 130 and the first conductive layerpattern 140 to cover the first external terminal 150. A ferrite materialor a ferromagnetic material may be used as the second insulation layer166.

Referring to FIG. 9, the second insulation layer 166 is partiallyremoved to form a second insulation structure 167 exposing at least aportion of the first external terminal 150.

Referring to FIG. 10, a portion of the second insulation structure 167,except for a portion of the second insulation structure 167 adjacent tothe first external terminal 150, is removed to form a second preliminaryinsulation layer pattern 168 having the protrusion 164 near the firstexternal terminal 150.

Referring to FIG. 11, the second preliminary insulation layer pattern168 is etched to form the second insulation layer pattern 160 having thethird opening 162 in communication with the second opening 134.Therefore, the second pad 114 of the semiconductor chip 110 is exposedthrough the second and the third openings 134 and 162.

Referring to FIG. 12, a second conductive layer 172 is formed on thesecond insulation layer pattern 160 and the second and the thirdopenings 134 and 162. In this example embodiment, a metal such asaluminum may be used as the second conductive layer 172.

Referring to FIG. 13, the second conductive layer 172 is partiallyremoved to form the second conductive layer pattern 170 that iselongated along the surface of the second insulation layer pattern 160from the second pad 114 to the surface of the protrusion 164. In thisexample embodiment, the second conductive layer pattern 170 has thefirst end connected to the second pad 114 and the second end on theprotrusion 164 elongated from the first end.

Referring to FIG. 14, a second external terminal 180 is formed on thesecond end of the second conductive layer pattern 170. The secondexternal terminal 180 may have a size substantially the same as that ofthe first external terminal 150. Examples of the second externalterminal 180 may include solder, gold, copper, etc and the secondexternal terminal 180 may be a conductive bump. Additionally, a reflowprocess may be performed on the second external terminal 180 to providethe second external terminal 180 with a spherical shape.

Finally, the wafer is cut along scribe lanes to complete thesemiconductor package 100 shown in FIG. 1. In this example embodiment,the semiconductor package 100 corresponds to a wafer-level package.

According to this example embodiment, as the first and the secondexternal terminals have the two-layered structure, the first and thesecond external terminals may be mounted on the pads of a board withoutan electrical short between the first and the second external terminals.

Example Embodiment 2

FIG. 15 is a cross-sectional view illustrating a semiconductor packagein accordance with the second example embodiment of the presentinvention.

A semiconductor package 200 of this example embodiment includes elementssubstantially the same as those of the semiconductor package 100 inEmbodiment 1 except for a ground terminal 250 and a second insulationlayer pattern 260. Thus, any further illustrations with respect to thesame elements are omitted herein for brevity.

Referring to FIG. 15, the semiconductor package 200 in accordance withthis example embodiment includes a semiconductor chip 210, a firstinsulation layer pattern 230, a first conductive layer pattern 240, aground terminal 250, a second insulation layer pattern 260, a secondconductive layer pattern 270 and a signal terminal 280.

A first pad 212 of the semiconductor chip 210 is used for ground, and asecond pad 214 is used for signal. Therefore, the ground terminal 250electrically connected to the first pad 212 is used for ground. As theground terminal 250 connected to the first pad 212 is used for ground,the ground terminal 250 has a width relatively wider than that of thesignal terminal 280 for rapidly transmitting an electric current.

Further, the second insulation layer pattern 260 does not have aprotrusion unlike the second insulation layer pattern 160 inEmbodiment 1. Therefore, the signal terminal 280 connected to the secondpad is formed on the second conductive layer pattern 270 on the secondinsulation layer pattern 260.

Here, a method of manufacturing the semiconductor package 200 inaccordance with this example embodiment is substantially the same asthat explained in Embodiment 1. Therefore, any further illustrationswith respect to the method are omitted herein for brevity.

According to example embodiments of the present invention, since theterminals have a stacked structure, a pitch between the terminals may benarrowed without an electrical short between the terminals. As a result,the semiconductor package having the terminals may have a small size.

Further, the pads of the board connected to the terminals may bealternately arranged around the slot of the board, so that the board mayhave a small size.

The foregoing is illustrative of the present invention and is not to beconstrued as limiting thereof. Although a few example embodiments of thepresent invention have been described, those skilled in the art willreadily appreciate that many modifications are possible in the exampleembodiments without materially departing from the novel teachings andadvantages of this invention. Accordingly, all such modifications areintended to be included within the scope of the present invention asdefined in the claims. Therefore, it is to be understood that theforegoing is illustrative of the present invention and is not to beconstrued as limited to the specific embodiments disclosed, and thatmodifications to the disclosed embodiments, as well as otherembodiments, are intended to be included within the scope of theappended claims. The present invention is defined by the followingclaims, with equivalents of the claims to be included therein.

1. A semiconductor package comprising: a semiconductor chip having afirst pad and a second pad; a first insulation layer pattern disposed onthe semiconductor chip, the first insulation layer pattern defining afirst opening exposing the first pad and a second opening exposing thesecond pad; a first conductive layer pattern disposed on the firstinsulation layer pattern and electrically connected to the first pad; afirst external terminal disposed on the first conductive layer pattern;a second insulation layer pattern disposed on the first conductive layerpattern and the first insulation layer pattern to expose the firstexternal terminal, the second insulation layer pattern defining a thirdopening in communication with the second opening; a second conductivelayer pattern disposed on the second insulation layer pattern andelectrically connected to the second pad; and a second external terminaldisposed on the second conductive layer pattern.
 2. The semiconductorpackage of claim 1, wherein the second external terminal is disposedhigher above the semiconductor chip than the first external terminal. 3.The semiconductor package of claim 2, wherein the second insulationlayer pattern has a protrusion higher than a surface of the firstexternal terminal, and the second external terminal is disposed on theprotrusion.
 4. The semiconductor package of claim 1, wherein the firstinsulation layer pattern and the second insulation layer patterncomprise a ferrite material or a ferromagnetic material.
 5. Thesemiconductor package of claim 1, wherein the first and the secondconductive layer patterns comprise aluminum.
 6. The semiconductorpackage of claim 1, wherein the first and the second external terminalscomprise solder, gold or copper.
 7. A method of manufacturing asemiconductor package, comprising: forming a first insulation layerpattern defining first and second openings that expose first and secondpads of a semiconductor chip, respectively, on the semiconductor chiphaving the first and second pads; forming a first conductive layerpattern on the first insulation layer pattern and the first pad; forminga first external terminal on the first conductive layer pattern; forminga second insulation layer pattern defining a third opening incommunication with the second opening on the first conductive layerpattern and the first insulation layer pattern, the second insulationlayer pattern exposing a portion of the first external terminal; forminga second conductive layer pattern on the second insulation layer patternand the second pad; and forming a second external terminal on the secondconductive layer pattern.
 8. The method of claim 7, wherein forming thefirst insulation layer pattern comprises: forming a first insulationlayer on the semiconductor substrate; and etching the first insulationlayer to form the first insulation layer pattern defining the first andthe second openings.
 9. The method of claim 8, wherein the firstinsulation layer comprises a ferrite material or a ferromagneticmaterial.
 10. The method of claim 7, wherein forming the firstconductive layer pattern comprises: forming a first conductive layer onthe first insulation layer pattern and the first opening; and etchingthe first conductive layer to form the first conductive layer pattern.11. The method of claim 10, wherein the first conductive layer comprisesaluminum.
 12. The method of claim 7, wherein forming the secondinsulation layer pattern comprises: forming a second insulation layer onthe first conductive layer pattern and the first insulation layerpattern so as to cover the first external terminal; partially removingthe second insulation layer to form a second insulation structure havinga protrusion higher than the first external terminal; and etching thesecond insulation structure to form the second insulation layer patterndefining the third opening.
 13. The method of claim 12, wherein thesecond insulation layer comprises a ferrite material or a ferromagneticmaterial.
 14. The method of claim 7, wherein forming the secondconductive layer pattern comprises: forming a second conductive layer onthe second insulation layer pattern, the second opening, and the thirdopening; and etching the second conductive layer to form the secondconductive layer pattern.
 15. The method of claim 14, wherein the secondconductive layer comprises aluminum.
 16. The method of claim 7, whereinthe first and the second external terminals comprise solder, gold orcopper.
 17. A semiconductor package comprising: a semiconductor chiphaving a ground pad and a signal pad; a first insulation layer patterndisposed on the semiconductor chip and defining a first opening and asecond opening that expose the ground pad and the signal pad,respectively; a first conductive layer pattern elongated along the firstinsulation layer pattern from the ground pad; a ground terminal disposedon the first conductive layer pattern; a second insulation layer patterndisposed on the first conductive layer pattern and the first insulationlayer pattern to partially expose the ground terminal, and defining athird opening in communication with the second opening; a secondconductive layer pattern elongated along the second insulation layerpattern from the signal pad; and a signal terminal disposed on thesecond conductive layer pattern.
 18. The semiconductor package of claim17, wherein the signal terminal is located higher above thesemiconductor chip than the ground terminal.
 19. The semiconductorpackage of claim 17, wherein the ground terminal has a width wider thanthat of the signal terminal.